ISO7816 asynchronous smart card information

For ISO7816 Standards Click HERE

This page presents the work carried out in the framework of a research project funded by the European Commission through the Esprit Program (EP8670) under the name "CASCADE " (Chip Architecture for smart cards and portable intelligent Devices).

smart cards are entering a dramatically growing number of service applications to take the place of money, tickets, documents and files. Credit card, cash-less pay phones, road toll systems, logical access control devices, health care files and pay TV are just a few of the current examples. All these applications need more and more intelligence inside the card to ensure an ever increasing level of security.

A traditional way to improve the smart card security consists of embedding more and more memory inside the component (to handle long size secrets) or adding to the 8-bit microprocessor of the card some powerful devices dedicated to cryptography.

But is cryptography the only way to make a card inviolable? What happens if the card is not used by its genuine owner? Today a simple PIN code verification is required to access the mine of secrets guarded inside the small piece of silicon. This weakness in the security scheme of the application cannot be solved with cryptography. New verification techniques, called biometric techniques, must be envisaged like voice or finger prints recognition.

These techniques require hard computation since a voice sample, for instance, is never exactly similar to its reference pattern, so a simple comparison is not suitable. The type of recognition algorithms are quite complex and completely different from those used for cryptography. So, on the one hand, an 8-bit microprocessor is not powerful enough to carry out the verification within reasonable time. On the other hand, cryptographic co-processors are unable to make it faster.

In addition to biometry, the emergence of generic smart card operating system based on Java!" technology, that means applications (or applets) running on top of a virtual machine let think that powerful processors have a key'role to play since interpretation of applets induces strong reduction in term of execution speed.

All these considerations make it clear that the silicon market for smart card is evolving in such a way many promising applications will come up against impassable barriers. The CASCADE approach, a drastically orthogonal approach consisting in introducing state of the art 32-bit RISC processor architecture in smart cards, will undoubtedly bring these brand new applications to maturity.

Microprocessors for Personal Computers start with 8-bit CISC architectures about 15 years ago. They have since progressed to 16-bit and to 32-bit engines and are now moving towards 64-bit architectures. In spite of the huge market, there has been no comparable evolution of the microprocessors used in smart cards. Existing smart cards use the same 8-bit (8051 or 6805 type) micro-controller cores as in the early beginnings, i.e. 15-year old chip designs.

Inside the CASCADE project framework, GEMPLUS has cooperated with ARM, UK-based architect of RISC processors with ideal features for portable devices: high performance, low power, small die size (APPLE has chosen ARM's RISC for its NEWTON Personal Digital Assistant also for these features). The processing power of an ARM RISC is approximately 100 times higher than used in current smart card chip implementations. The capability of handling 32-bit data words will significantly improve the speed for the processing of complex calculations. In addition, state of the art high level programming language compilers are available for ARM processors, whereas old 8-bit CISC processors have only inefficient compilers. An important increase of performance can thus be expected due to higher efficiency of code.

Moreover, the architecture designed by ARM brings new opportunities in the smart card area not conceivable with current 8-bit processors. The design allows indeed interrupt management enabling customized answers to physical attacks (the security sensors raise a software interrupt which is quite easy to modify). A dynamic clock multiplier enables very fast internal frequency to speed up some specific processing requiring long computations. Last, an " halt-mode " is available to reduce significantly the consumption in case of wait state of the chip.

Texas Instruments, who licensed the chip design, will provide the component to be used in smart cards and other secure portable electronic devices. This component, in addition to the strong advantages offered by the processor, will allow wide-voltage (supply voltage: 5V-3V) to focus also on GSM applications.

To illustrate the chip possibilities, NOKIA realized a feasibility study on a banking application working in cooperation with a pro-active SIM application to perform a balance inquiry on an external banking system via the Short Message Service channel of the GSM mobile.

DASSAULT Automatismes et Telecommunications worked on the normalization and conformance testing aspects for this new kind of devices.

Cryptography

Most of today's security mechanisms in smart card applications are based on symmetric functions using shared secrets. This makes trans-national applications and multi-application systems very difficult to implement, because of the reluctance of application providers to share secrets with potential competitors.

Switching to asymmetric functions not requiring the sharing of secrets is therefore essential to be able to implement "open" cryptographic applications. Being able to do this, whilst matching the speed requirements of acceptable Man Machine Interfaces (MMI) requires better software implementations of these functions to be carried out on faster processors.

Adding security in the form of co-processing units that can be attached as peripherals or mounted inside the kernel of the portable computers is the common solution to reach that goal. But this solution is far from satisfactory because of its strong dependence from the hardware which make it too rigid. A 32-bit RISC smart card processor will be able to handle such calculations much more efficiently while retaining the flexibility of a general-purpose engine.

The University of Louvain-la-Neuve (UCL Crypto Group) has implemented a library of the most commonly used cryptographic algorithms especially optimized for the ARM processor giving very encouraging results (see figures in annex).

Biometry

For consistent security, a smart card shall be used only by its genuine owner. As mentioned in the introduction, PIN code verification alone is not considered satisfactory as it is intrinsically weak. Consequently, positive identification of the card owner by biometric means is a necessity now. For privacy and security'reasons, the biometric recognition must be handled locally by the smart card. The " template ", i.e. the biometric reference pattern of the card holder is one of the secrets to be held permanently in the memory of the card.

Implementing biometric verification inside a smart card is notoriously difficult since templates tend to eat-up a large part of the card memory while biometric verification algorithms are beyond the processing capabilities of standard processors.

Voice recognition has been selected as the most suitable biometric technology for the project. The technology has been developed by UK based Domain Dynamics Limited and Neural Computer Sciences providing efficient voice digitization and customized artificial neural network for the recognition.

The introduction of biometry will provide a level of security previously unattainable, with inviolable protection against fraud. This will open the use of smart cards to new applications with higher security constraints. CASCADE is the first smart card chip to introduce sophisticated biometrics features in low cost mass-market applications.

Generic smart card Operating System

Generic smart cards are smart cards that look like PCs. They do not have any application-oriented functions in their basic functionalities. Consequently, the smart card program is a real operating system which role is to manage the smart card hardware resources for smart card applications. Applications are not pre-defined, they can be dynamically downloaded. The smart card operating system allocates memory for storing application data and activates application functions on reception of commands. For security'reasons inherent to smart card micro-controllers (embedded chip containing a microprocessor and memories), application functions are run on top of a virtual machine by a secure interpreter rather than directly in native language.

An important drawback of virtual machines is of course the reduced execution speed. This is easily overcome by a powerful processor such as the ARM, since code interpreted by this engine will be faster than native code executed by today's 8-bit processors. A 32-bit RISC smart card processor will allow smaller, more secure and more portable application code to be written.

The work on this topic has been performed jointly by GEMPLUS and the University of Lille. GEMPLUS is now looking forward to develop compatible Java!" platform for smart cards. These future developments will surely benefit of the powerful CASCADE architecture. The OS will also have the ability of software compression/decompression. This part is provided by the UCL Crypto Group.

First card samples
Q3 1997

Small quantities
Q4 1997

Volume Production
Q1 1998


The ARM7TDM processor

32-bit RISC processor (32-bit data & address bus)
Big and Little Endian operating modes
High performance RISC 17 MIPS sustained @ 25 MHz (25 MIPS peak) @ 3V
Simple but powerful instructions sets (16 & 32-bit)
Register to register architecture
Low power consumption
Fast interrupt response for real-time applications
Excellent high-level language support

The CASCADE card

Memory Configuration

Static RAM 512 bytes
Boot ROM 8K bytes
Program FLASH 16K bytes
Data FLASH 16K bytes

Operating Features

Operation Voltage (Vcc): 5V-3V ? 10%
External Clock Frequency: 3-5MHz
HALT Low-Power Mode
Temperatures Ranges: 0?C to +85?C

I/O Communications

Speed up to 115 kbps
T=0 protocol (ISO/IEC 7618-3)

Compliance with Standards

ISO/IEC 7816-1, -2, -3

PC-Based Workstation Development

Real-time Emulation
Symbolic Debug
Extensive Breakpoint/Trace Capability
" C " programming language

Figures about cryptographic functions implementation

RSA signature with CRT (512 bits) 72 ms

RSA signature with CRT (768 bits) 223 ms

RSA signature with CRT (1024 bits) 488 ms

DSS signature (512 bits) 94 ms

DSS verification (512 bits) 125 ms

SHA (512 bits) 0.35 ms

Key Generation (512 bits) less than 1 minute

DES (with precomputed keys) 507 kbps